CMOS IP CORES

Phase Locked Loop

RIBPL01

The RIBPL01 is a low power and fast locking phase lock loop 0.18um Silicon CMOS process technology to obtain high frequency operating both in the phase comparator and VCO sections.The PLL provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip VCO. The on-chip VCO tunes from 2000 MHz to 2800 MHz.

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Low Speed, low power Receiver IP for PHY

RCLRX01

The RCLRX01 is low power, low voltage Receiver IP designed using 0.18um CMOS process. It can be configured and interfaced within various PHY ICs using multilevel signaling to perform the controlling functions. It can receive the low frequency control signals to various other PHY blocks. The Low-Power Receiver is a slew-rate controlled push-pull driver. It supports 20Mbps speed.

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Low Speed, low power Transmitter IP for PHY

RCLTX01

The RCLTX01 is low power, low voltage Transmitter IP designed using 0.18um CMOS process. It can be configured and interfaced within various PHY ICs using multilevel signaling to perform the controlling functions. It can receive the low frequency control signals to various other PHY blocks. The Low-Power Transmitter is a slew-rate controlled push-pull driver. It supports 20Mbps speed.

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High Speed Differential Signal Receiver IP for PHY

RCRX01

The RCRX01 is LVDS receiver IP designed using 0.18um CMOS process. It can be configured and interfaced within various PHY ICs using multilevel signaling and supports data or clock signals reception up to 1Gbps (max). The LVDS receiver accepts differential input levels and translates them into standard single ended output. The receiver receives High-Speed data correctly while rejecting common-mode interference. During operation of the receiver, termination impedance is required between the DP and Dn pins of the receiver.

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High Speed Differential Signal Transmitter IP for PHY

RCTX01

The RCTX01 is LVDS Transmitter IP designed using 0.18um CMOS process. It can be configured and interfaced within various PHY ICs using multilevel signaling and supports data or clock signals reception up to 1Gbps (max). The LVDS Transmitter accepts differential input levels and translates them into standard single ended output. The Transmitter Transmit High-Speed data correctly while rejecting common-mode interference. During operation of the Transmitter, termination impedance is required between the DP and Dn pins of the Transmitter.

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Low Power Voltage Reference

RFVGR03

Low-cost series voltage references meets the cost advantage of shunt references and offers the power-saving advantage of series references, which traditionally cost more.These low power, low-cost devices are ideal for high-volume, cost-sensitive 1.8V battery operated systems with wide variations in supply voltage that require very low power dissipation.

Key Features.                      

  • 2.1 % Max. initial Accuracy
  • 71 ppm/°C max. temperature Coefficient
  • Low Power Consumption
  • Power-up and Power-down mode available
  • No external Capacitor required
  • Fast Settling time
  • Low Power Dissipation

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Low Dropout Regulator

RJLDO03                         

The RJLDO03, Low Dropout Regulator is ideal for systems where a low cost solution is critical. This device features extremely low quiescent current which is typically 5uA. Dropout voltage is also very low, typically 600mV. The RJLDO03 has an Enable pin feature, which when pulled low will enter the LDO regulator into a shutdown mode removing power from its load and offering extended power conservation capabilities for portable battery powered applications. The devices have been optimized to meet the needs ofModern wireless communications design; Low noise, low Dropout, small size, high peak current, high noise immunity.The device is rated over a -40°C to +125°C temperature range. Since only, 18uF ceramic output capacitor is recommended, the RJLDO03 is a truly cost effective voltage conversion solution. This Building block is designed in 180nm CMOS technology.

Key Features.                       

  • 600 mV Low Dropout Voltage
  • 5 uA Quiescent Current
  • 40 mA average output Current
  • 2.1% High Accuracy
  • < 100 ppm/ 0C Low Temperature Coefficient
  • Power-Saving Shutdown Mode
  • Low Power Consumption
  • Operating Junction Temperature Range   -40°C to +125°C

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Dual Modulus Programmable Frequency Divider                                                                                                                   

A low-power high-speed programmable dual modulus divider data-sheet is presented. The circuit's three building blocks: prescaler, 2-bit and 5-bit programmable dividers; were designed using high-performance single-phase clocking latchup circuits rather than the conventional latchup circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 16 - 127. The programmable dual-modulus divider with 1.5 GHz maximum operating frequency was designed using the 0.18-um CMOS technology. Post parasitic-extracted layout results verify that the total power dissipation was 1.8 mW (at 1.5 GHz, 1.8 V).

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Low Noise Amplifier: RTLNA01

The RTLNA01 is Low Noise Amplifier. The device is designed for 802.11 b/g.
Frequency range : 2 to 4 GHz
Supply Voltage/Current : ±3V/7.5mA
Noise Figure : 1.5dB @ 2 GHz

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Driver Amplifier: RTDA01

The RTDA01 is CMOS driver amplifier. The device is designed for the 802.11 a/b/g WLAN systems.
Frequency range : 2 to 5 GHz
Supply Voltage/Current : ±3.3V/192.4mA

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Voltage Controlled Oscillator

VCO: RJVC01

RJVC01 is voltage controlled oscillator.The RJVC01 has designed on the CMOS 0.18 um Process. The die area is very small.
Frequency range : 0.5 to 1.15 GHz
Supply Voltage/Current : ±1.2V/2.5mA

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VCO: RJVC02

RJVC02 is voltage controlled oscillator.The RJV02 has designed on the CMOS 0.18 um Process.
Frequency range : 2 to 6 GHz
Supply Voltage/Current : ±1.8V/1mA

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Ring Oscillator

RG01

The RG01 is a Ring Oscillator for wide band, Low Phase Noise. In this Ring oscillator frequency range is from 2.2 to 2.8 GHz. The Ring Oscillator designed using the  0.18um CMOS technology. Post parasitic-extracted layout results verify that the total power dissipation was 1.8 mW (at 2.8 GHz, 1.8 V). In this Ring Oscillator we have used Band Gap Reference to minimize the frequency Drift with temperature and supply variations.

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PHASE FREQUENCY DETECTOR (PFD)

RIBFD01

A low-power Phase Frequency detector (PFD) data-sheet is presented. The circuit’s building blocks: two D Flip -Flop, inverter and NAND gate for reset Flip-Flop; were designed using high-performance Dead –Zone free circuit. The D Flip-Flop compare input frequency and Divided Frequency with phase and frequency. If input frequency is greater than divided frequency compare output is present at upper D Flip-Flop and lower D Flip-Flop output is “0”. Similarly   If input frequency is lower than divided frequency compare output is present at lower D Flip-Flop and upper D Flip-Flop output is “0”.Phase frequency Detector was designed using the 0.18-um CMOS technology.

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